High performance SRAMs in 1.5 V, 0.18 /spl mu/m partially depleted SOI technology

Author

Joshi, R.V. ; Pellela, A. ; Wagner, O. ; Chan, Y.H. ; Dachtera, W. ; Wilson, S. ; Kowalczyk, S.P.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

2002

fDate

13-15 June 2002

Firstpage

74

Lastpage

77

Abstract

This paper describes high speed SRAMs with read access time below 500 ps and a cycle time around 2 GHz in 1.5 V, 0.18 /spl mu/m partially depleted (PD) SOI CMOS technology. The paper also provides the robust designs to improve performance and functionality in PD SOI. The highlights of the paper are optimized timing for pseudostatic circuits, novel design of the sense amplifier, design techniques to improve functionality and performance at high temperatures and cell stability. Also a full functional SRAM (Directory, L1 Cache and other SRAMs) hardware with high yields is demonstrated by providing extensive test pattern coverage generated by a programmable "Array-Built-In-Self-Test" (ABIST).

Keywords

CMOS memory circuits; SRAM chips; VLSI; built-in self test; circuit stability; high-speed integrated circuits; high-temperature electronics; integrated circuit testing; silicon-on-insulator; timing; 0.18 micron; 1.5 V; 2 GHz; 500 ps; Si; array-built-in-self-test; design techniques; dynamic cell stability; high performance SRAMs; high temperatures; high yields; optimized timing; partially depleted SOI CMOS technology; programmable array BIST; pseudostatic circuits; robust designs; sense amplifier; static RAMs; test pattern coverage; CMOS technology; Circuit stability; Circuit testing; Design optimization; Hardware; Random access memory; Robustness; Temperature sensors; Test pattern generators; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits Digest of Technical Papers, 2002. Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-7310-3

Type

conf

DOI

10.1109/VLSIC.2002.1015050

Filename

1015050