• DocumentCode
    1902906
  • Title

    Electrostatic effect of localised charge in dual bit memory cells with discrete traps

  • Author

    Perniola, L. ; Bernardini, S. ; Iannaccone, G. ; De Salvo, B. ; Ghibaudo, G. ; Masson, P. ; Gerardi, C.

  • Author_Institution
    Dipt. di Ingegneria dell´´Informazione, Universita degli Studi di Pisa, Italy
  • fYear
    2004
  • fDate
    21-23 Sept. 2004
  • Firstpage
    249
  • Lastpage
    252
  • Abstract
    In this paper, the electrostatic impact of channel hot electron (CHE) injection in discrete-trap memories is quantitatively addressed. The dual bit behavior of the transfer characteristics during forward and reverse read of a written cell is thoroughly analysed with the help of an analytical model. Such a model allows, for the first time, to estimate the effective charged portion of the discrete storage layer, L2, and the quantity of electrons, Q, injected in the trapping sites from the experimental parameters of the Id-Vg characteristics, the reverse-forward threshold voltage shift ΔVRF, and the total threshold voltage shift ΔVtot. The viability of this model is confirmed with tests performed on nanocrystal memories, under different bias conditions. These results are confirmed with the help of a 2D drift-diffusion commercial code (ATLAS-SILVACO).
  • Keywords
    electron traps; electrostatics; hole traps; hot carriers; nanoelectronics; random-access storage; semiconductor device models; 2D drift-diffusion model; MOSFET channel threshold voltage; channel hot electron injection; discrete storage layer effective charged portion; discrete trap memory cells; dual bit memory cells; localised charge electrostatic effects; nanocrystal memory bias conditions; nonvolatile discrete-trap memory products; reverse-forward threshold voltage shift; trapping sites; written cell forward read; written cell reverse read; Analytical models; Channel hot electron injection; Conductivity; Electron traps; Electrostatics; Integrated circuit modeling; Nanocrystals; Performance evaluation; Testing; Threshold voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Device Research conference, 2004. ESSDERC 2004. Proceeding of the 34th European
  • Print_ISBN
    0-7803-8478-4
  • Type

    conf

  • DOI
    10.1109/ESSDER.2004.1356536
  • Filename
    1356536