Modeling of STI-induced stress phenomena in CMOS 90nm Flash technology

Author

Fantini, P. ; Giuga, G. ; Schippers, S. ; Marmiroli, A. ; Ferrari, G.

Author_Institution

STMicroelectronics, Agrate Brianza, Italy

fYear

2004

fDate

21-23 Sept. 2004

Firstpage

401

Lastpage

404

Abstract

A non negligible layout sensitivity of MOSFETS electrical behavior has been recently observed in advanced CMOS technologies. Some efforts have been attempted to encapsulate this phenomenon in Spice-like simulation oriented models. In the present work, we suggest improvements to previously proposed approaches, after a critical discussion about them. An extensive characterization of CMOS 90 nm Flash memory technology is the support of our issues. Finally, simulation of prototype circuits shed some light on the impact of STI stress in IC design.

Keywords

CMOS memory circuits; MOSFET; flash memories; integrated circuit design; integrated circuit modelling; internal stresses; isolation technology; semiconductor device models; 90 nm; CMOS; Flash memory; IC design; MOSFET electrical behavior layout sensitivity; STI-induced stress; Spice-like simulation models; CMOS technology; Circuit testing; Compressive stress; Isolation technology; MOSFETs; Prototypes; Semiconductor device modeling; Silicon; Thermal expansion; Ultra large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research conference, 2004. ESSDERC 2004. Proceeding of the 34th European

Print_ISBN

0-7803-8478-4

Type

conf

DOI

10.1109/ESSDER.2004.1356574

Filename

1356574