The resource conflict methodology for early-stage design space exploration of superscalar RISC processors

In this paper we propose a new execution trace driven simulation technique, called the Resource Conflict Methodology (RCM) for modeling and simulating computer systems early in the design cycle. By using a simplified hardware element model which allows the user to easily add or delete hardware elements in the model, RCM allows the user to readily change the machine design being investigated and to evaluate the resulting machine on a given workload. We describe the RCM model with reference to a family of superscalar processors and develop an RCM-based analysis program (called REAP) for this family of processors. Using REAP, we demonstrate the validity of our method by comparing its RCM performance estimates to those of a traditional early design stage timer model