Macro-instruction generation for dynamic logic caching

Author

McCarley, Kendel ; Vrudhula, Sarma B K

Author_Institution

Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA

fYear

1997

fDate

24-26 Jun 1997

Firstpage

63

Lastpage

69

Abstract

This paper outlines the synthesis of macro-instructions for dynamically reprogrammable FPGAs so that they may be easily generated, placed, and garbage collected at run-time. An overview of a dynamic logic caching computer that uses these macro-instructions is given and their use within the´s environment discussed. The synthesis of macro-instructions is illustrated with a basic example. Finally, the current state of development of a logic cache based computing platform and compiler/simulator workframe is presented

Keywords

cache storage; field programmable gate arrays; high level synthesis; macros; compiler/simulator workframe; dynamic logic caching; dynamically reprogrammable FPGAs; logic cache based computing platform; macro-instructions; Computer aided instruction; Coprocessors; Field programmable gate arrays; Hardware; Logic arrays; Programmable logic arrays; Random access memory; Read-write memory; Reconfigurable logic; Runtime;

fLanguage

English

Publisher

ieee

Conference_Titel

Rapid System Prototyping, 1997. Shortening the Path from Specification to Prototype. Proceedings., 8th IEEE International Workshop on

Conference_Location

Chapel Hill, NC

ISSN

1074-6005

Print_ISBN

0-8186-8064-4

Type

conf

DOI

10.1109/IWRSP.1997.618827

Filename

618827