3D IC Process integration challenges and solutions

In this paper the process integration challenges for a 3-D die to wafer stacking technology are investigated. A process for etching through the full multi layer field dielectric of a completed wafer is achieved. Ionized PVD is used to form a barrier and liner, and is shown to allow full metal coverage of scallops and undercut resulting from the combined deep silicon via etch and oxide liner deposition processes. Void free copper plating of the completed via is demonstrated to verify successful integration of all stages necessary for through silicon via formation.