DocumentCode
1905450
Title
Pipelined architecture for fast IP lookup
Author
Zhao, Ting ; Lea, Chin-Tau ; Huang, Ho-Chi
Author_Institution
Dept. of EEE, Hong Kong Univ. of Sci. & Technol., Kowloon, China
fYear
2005
fDate
12-14 May 2005
Firstpage
118
Lastpage
122
Abstract
IP lookup is a key step in IP processing and many algorithms have been proposed. The challenges are speed, fast table updates, cost and power consumption. In this paper, we propose a RAM-based architecture for IP lookup. The design requirements are the following: one memory access per lookup, reasonable amount of memory requirement, and fast table updates. We show the design and its performance in the paper.
Keywords
IP networks; pipeline processing; random-access storage; table lookup; IP lookup; RAM-based architecture; memory access; pipelined architecture; CADCAM; Computer aided manufacturing; Costs; Data structures; Energy consumption; Hardware; Random access memory; Routing; Search engines; Table lookup;
fLanguage
English
Publisher
ieee
Conference_Titel
High Performance Switching and Routing, 2005. HPSR. 2005 Workshop on
Print_ISBN
0-7803-8924-7
Type
conf
DOI
10.1109/HPSR.2005.1503206
Filename
1503206
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