DocumentCode
1906698
Title
VLSI prototyping of low-complexity wavelet transform on FPGA
Author
Alam, Mehboob ; Onen, Denis ; Badawy, Wael ; Jullien, Graham
Author_Institution
Dept. of Electr. & Comput. Eng., Calgary Univ., Alta., Canada
Volume
1
fYear
2002
fDate
2002
Firstpage
412
Lastpage
415
Abstract
In this paper, a low-complexity architecture using lifting step is proposed. The architecture makes use of existing lifting scheme and strategically schedules the MAC (multiplier adder cell) for its optimum use. It has been shown that the number of multiplier and adder are reduced to one half for implementing a lifting step. The proposed approach can be extended to other wavelet transforms implemented via lifting and it can be shown that better results are achieved
Keywords
VLSI; adders; circuit CAD; field programmable gate arrays; integrated circuit design; logic CAD; multiplying circuits; wavelet transforms; FPGA; MAC; VLSI prototyping; lifting step; low-complexity wavelet transform; multiplier adder cell; Computational complexity; Computer architecture; Design engineering; Discrete wavelet transforms; Field programmable gate arrays; Filter bank; Processor scheduling; Prototypes; Very large scale integration; Wavelet transforms;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical and Computer Engineering, 2002. IEEE CCECE 2002. Canadian Conference on
Conference_Location
Winnipeg, Man.
ISSN
0840-7789
Print_ISBN
0-7803-7514-9
Type
conf
DOI
10.1109/CCECE.2002.1015260
Filename
1015260
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