Performance of a full-hardware PTP implementation for an IEC 62439-3 redundant IEC 61850 substation automation network

Author

Kirrmann, Hubert ; Honegger, Claudio ; Ilie, Diana ; Sotiropoulos, Ioannis

Author_Institution

ABB Res. Center, Baden, Switzerland

fYear

2012

fDate

24-28 Sept. 2012

Firstpage

1

Lastpage

6

Abstract

Seamless redundancy and precise clock synchronization are integrated fully in hardware (FPGA) with no processor support. The interaction between redundancy and clock synchronization is explained. Redundant synchronization messages are not be discarded, but used to improve clock accuracy. Measurement results confirm the validity of the concept. Performance of the full-hardware implementation is compared with that of a conventional software-hardware implementation.

Keywords

IEC standards; field programmable gate arrays; protocols; redundancy; substation automation; synchronisation; FPGA; IEC 62439-3 redundant IEC 61850 substation automation network; clock synchronization; full-hardware PTP implementation; parallel redundancy protocol; redundant synchronization messages; Clocks; Delay; IEC standards; Peer to peer computing; Redundancy; Synchronization; FPGA; HSR; IEC 61588; IEC 61850; IEC 62439-3; IEEE 1588; PRP; clock redundancy; power profile;

fLanguage

English

Publisher

ieee

Conference_Titel

Precision Clock Synchronization for Measurement Control and Communication (ISPCS), 2012 International IEEE Symposium on

Conference_Location

San Francisco, CA

ISSN

1949-0305

Print_ISBN

978-1-4577-1714-7

Type

conf

DOI

10.1109/ISPCS.2012.6336631

Filename

6336631