Minimal test configurations for FPGA local interconnects

Author

Sun, X. ; Xu, J. ; Alimohammad, A. ; Trouborst, Pieter

Author_Institution

Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta., Canada

Volume

1

fYear

2002

fDate

2002

Firstpage

427

Abstract

This paper presents a built-in self-test (BIST) technique for testing local interconnects of field programmable gate arrays (FPGAs). To maximize the parallel testing, we use error control coding to test one portion of interconnects and functional test of D flip-flops to verify the integrity of another portion of interconnects in a test configuration (TC). We introduce a heuristic method for deriving minimal interconnect TCs by modeling local interconnects with adjacency graphs, then solving the graph coloring problems. The proposed scheme has superior multiple fault coverage.

Keywords

built-in self test; error correction codes; fault location; field programmable gate arrays; flip-flops; graph colouring; integrated circuit interconnections; integrated circuit reliability; integrated circuit testing; logic testing; BIST; D flip-flop functional test; FPGA local interconnects; adjacency graphs; built-in self-test technique; error control coding; field programmable gate arrays; graph coloring; graph coloring problems; in-system testing; interconnect integrity; minimal interconnect test configuration; minimal test configurations; multiple fault coverage; parallel testing; parity-checking; Application specific integrated circuits; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Error correction; Field programmable gate arrays; Flip-flops; Integrated circuit interconnections; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 2002. IEEE CCECE 2002. Canadian Conference on

ISSN

0840-7789

Print_ISBN

0-7803-7514-9

Type

conf

DOI

10.1109/CCECE.2002.1015263

Filename

1015263