• DocumentCode
    190693
  • Title

    Modeling dynamic partial reconfiguration in the dataflow paradigm

  • Author

    Piat, Jonathan ; Crenne, Jeremie

  • Author_Institution
    LAAS, Toulouse, France
  • fYear
    2014
  • fDate
    20-22 Oct. 2014
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    An important number of studies have shown the benefit of dynamic partial reconfiguration in reconfigurable computing. Signal processing applications can make use of this technology in such a way that it allows greater flexibility, performances and cost reduction. However several points still need to be addressed and represent critical challenges. One of them concerns architectures modeling as abstraction is strongly required to help designers in building efficient designs. Dataflow is a well adopted modeling paradigm for signal processing application to allow early stage system properties evaluation. This paper describes a first attempt to model dynamic partial reconfiguration in the dataflow paradigm. Our proposal leads to an efficient and simple approach suitable for signal processing systems.
  • Keywords
    digital signal processing chips; field programmable gate arrays; reconfigurable architectures; DPR; dynamic partial reconfiguration; field-reconfigurable computing; signal processing systems; Computational modeling; Data models; Field programmable gate arrays; Production; Schedules; Signal processing; Unified modeling language;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Signal Processing Systems (SiPS), 2014 IEEE Workshop on
  • Conference_Location
    Belfast
  • Type

    conf

  • DOI
    10.1109/SiPS.2014.6986103
  • Filename
    6986103