Design theory and fabrication process of 90nm unipolar-CMOS

Author

Lin, Jyi-Tsong ; Chen, Hsuan-Hsu ; Lu, Kuan-Yu ; Sun, Chih-Hung ; Eng, Yi-Chuen ; Kuo, Chih-Hao ; Lin, Po-Hsieh ; Lai, Tung-Yen ; Yang, Fu-Liang

Author_Institution

Dept. of Electr. Eng., Nat. Sun Yat Sen Univ., Kaohsiung, Taiwan

fYear

2010

fDate

13-14 June 2010

Firstpage

1

Lastpage

2

Abstract

The innovative basic punchthrough theory for the unipolar-CMOS is for the first time presented and the first unipolar-CMOS inverter has been fabricated successfully by using the 90nm technology developed in Taiwan National Nano Device Lab. The severe scaling issues with silicon can be further use and no more serious. The low-performance P-FETs can be get rid of and switch much faster both for high-electron-mobility III-V and CNT based technology. According to the measurement two empirical models, the new concept of the load line drawing and the optimum design of the unipolar-CMOS are also illustrated. Employing them for unipolar-CMOS design, the desired high performance ultimate SOC and SOP system can be easily realized.

Keywords

CMOS integrated circuits; III-V semiconductors; high electron mobility transistors; invertors; power field effect transistors; silicon; CNT based technology; SOC system; SOP system; Si; Taiwan National Nano Device Lab; fabrication process; high-electron-mobility III-V technology; low-performance P-FET; size 90 nm; unipolar-CMOS inverter; CMOS integrated circuits; Current measurement; Fabrication; Load modeling; Logic gates; MOS devices; Semiconductor device measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Silicon Nanoelectronics Workshop (SNW), 2010

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4244-7727-2

Electronic_ISBN

978-1-4244-7726-5

Type

conf

DOI

10.1109/SNW.2010.5562542

Filename

5562542