A technique for low power testing of VLSI chips

Power consumption of a circuit is more in test mode than normal mode. The increased heat due to excess power dissipation can open up reliability issue due to electro-migration. In extreme conditions excess power consumption might even result in chip burn outs also. In this paper, we propose a scan flip-flop which helps to reduce the power consumption during test mode without affecting the functional mode requirements. The proposed scan flip-flop use the single latch double edge triggered flip-flop to perform the scanning during test by halving of number of cycles in the clock frequency. The proposed design of clock driving circuit for the scan flip-flop helps to use the same flip-flop during the normal mode for the specified clock frequency. This avoids the redesign of the circuit for normal mode while using the high speed proposed scan flip-flop. The usage of the proposed scan flip-flop reduces the silicon area by 30% - 45% and the power dissipation by 25% - 35%.