DocumentCode
1907805
Title
Analysis of SCEs in nanoscale FinFET with high-k gate dielectric
Author
Xie, Qian ; Xu, Jun
Author_Institution
Tsinghua Nat. Lab. for Inf. Sci. & Technol., Tsinghua Univ., Beijing, China
fYear
2010
fDate
13-14 June 2010
Firstpage
1
Lastpage
2
Abstract
We derive a three-dimensional (3-D) analytical model of scale length for nanoscale SOI tri-gate FET (SOI-FinFET) and discuss its significance. This work takes into account the difference in permittivity between the fin (channel) and the gate insulator, and thus permits this model accurate for the analysis of SCEs in nanoscale FinFET with high-k gate dielectric. Based on the theory, we analyze the effects of geometrical dimensions and materials on the SCEs in nanoscale FinFET.
Keywords
MOSFET; silicon-on-insulator; gate insulator; high-k gate dielectric; nanoscale SOI trigate FET; short channel effect; Analytical models; FinFETs; Insulators; Logic gates; Materials; Nanoscale devices; Permittivity;
fLanguage
English
Publisher
ieee
Conference_Titel
Silicon Nanoelectronics Workshop (SNW), 2010
Conference_Location
Honolulu, HI
Print_ISBN
978-1-4244-7727-2
Electronic_ISBN
978-1-4244-7726-5
Type
conf
DOI
10.1109/SNW.2010.5562569
Filename
5562569
Link To Document