VLSI signal processing oriented segmentation based serial parallel multiplier

In this paper a novel VLSI SP oriented architecture for implementation of serial parallel Multipliers (SPM) is proposed. The VLSI oriented multiplier is based on a segmentation technique of SPM and the conventional full adders are replaced by low power full adder. In this paper two architectures namely Segmented Based SPM, Folded VLSI oriented segmented based SPM are compared for power and area. The proposed VLSI SP oriented architecture achieves higher throughput and less area compared to the segmentation based serial parallel multiplier proposed [1]. The proposed VLSI SP oriented architecture permits the optimization of the area, speed and power.