A generalized HSPICE macro-model for pseudo-spin-valve GMR memory bits

Nonvolatile semiconductor storage using Giant-Magneto-Resistance (GMR) memory bits has the potential for revolutionizing both high density and high speed memory applications with devices exhibiting unlimited write endurance and very low required write energy. This work presents the first generalized circuit macro-model for a pseudo-spin valve GMR memory bit. The macro-model is realized as a four terminal sub-circuit which emulates GMR bit behavior over a wide range of sense and word line currents. The nonvolatile and nonlinear nature of GMR memory bits are accurately represented by this model and simulations of nonvolatile GMR latch structures with HSPICE show expected outcomes. The model is flexible and relatively simple: ranges of the write/read currents and bit resistance values are incorporated as parameterized variables and no semiconductor devices are used within the model