50 nm-Gate All Around (GAA)-Silicon On Nothing (SON)-devices: a simple way to co-integration of GAA transistors within bulk MOSFET process

Author

Monfray, S. ; Skotnicki, T. ; Morand, Y. ; Descombes, S. ; Coronel, P. ; Mazoyer, P. ; Harrison, S. ; Ribot, P. ; Talbot, A. ; Dutartre, D. ; Haond, M. ; Palla, R. ; Le Friec, Y. ; Leverd, F. ; Nier, M.-E. ; Vizioz, C. ; Louis, D.

Author_Institution

R&D France Telecom, Grenoble, France

fYear

2002

fDate

11-13 June 2002

Firstpage

108

Lastpage

109

Abstract

For the first time, both GAA and bulk devices were shown to be operational on the same chip. Not all issues have been solved yet (gate materials, access resistance) but already the first-try results are very encouraging: I/sub on/=170 /spl mu/A//spl mu/m@1.2 V and gate oxide of 20 /spl Aring/. Thanks to the GAA intrinsic immunity to SCE, its DIBL was as small as 10 mV compared with 600 mV on bulk control devices. Calibrating a 2D simulator on this electrical data, the performance of the GAA was estimated to be at least 1500 /spl mu/A//spl mu/m@ 1 V with comfortable gate oxide of 20 /spl Aring/, once having corrected for the large R/sub access/ (/spl sim/3000 /spl Omega/), that was simply due to non-optimal mask layout used in this first device realization.

Keywords

MOSFET; semiconductor technology; 1 V; 1.2 V; 20 A; 2D simulator; 50 nm; 50 nm-gate all around-silicon on nothing devices; DIBL; Si; Si-SiO/sub 2/; access resistance; bulk MOSFET process; co-integration; gate materials; gate oxide; nonoptimal mask layout; short-channel effect immunity; Degradation; Etching; Extremities; Germanium silicon alloys; MOSFETs; Paper technology; Semiconductor device measurement; Silicon germanium; Solid modeling; Surface morphology;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-7312-X

Type

conf

DOI

10.1109/VLSIT.2002.1015411

Filename

1015411