Vertical pass transistor design for sub-100 nm DRAM technologies

Author

McStay, K. ; Chidambarrao, D. ; Mandelman, J. ; Beintner, J. ; Tews, H. ; Weybright, M. ; Wang, G. ; Li, Y. ; Hummler, K. ; Divakaruni, R. ; Bergner, W. ; Crabbe, E. ; Bronner, G. ; Mueller, W.

Author_Institution

Infineon Technol., Hopewell Junction, NY, USA

fYear

2002

fDate

11-13 June 2002

Firstpage

180

Lastpage

181

Abstract

The 8F/sup 2/ vertical transistor DRAM cell is a cost-efficient, litho-friendly structure suitable for scaling to sub-100 nm ground rules. In this paper, we report on device design considerations for vertical pass transistors used in ultra-dense DRAM technologies. A double-gate, vertical DRAM pass transistor that meets 1fA off-current requirement and offers twice the current drive of comparable 175 nm planar devices will be presented. Additionally, structural features unique to vertical devices are highlighted.

Keywords

CMOS memory circuits; DRAM chips; MOSFET; doping profiles; semiconductor technology; 1 fA; 100 nm; 8F/sup 2/ vertical transistor DRAM cell; channel engineering; current drive; device design considerations; dopant profiles; double-gate vertical DRAM pass transistor; litho-friendly structure; off-current requirement; source/drain engineering; structural features; sub-100 nm DRAM technologies; sub-100 nm ground rules; ultra-dense DRAM technologies; vertical pass transistor design; Capacitors; Degradation; Doping; Implants; Leakage current; Microelectronics; Power engineering and energy; Process design; Random access memory; Research and development;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-7312-X

Type

conf

DOI

10.1109/VLSIT.2002.1015443

Filename

1015443