Modeling Failure Reduction for Combinational Logic using Gate Level NMR

We present a mathematical model for describing the relationship between overhead and error reduction under single-error conditions in combinational logic using N-modular redundancy (NMR) as an upper bound. We then provide an analysis for the model under more realistic circuit and overhead assumptions. We compare system, sub-circuit, and gate level NMR. Based on our results, implementing NMR at the gate level offers the benefits of NMR with customizable overheads but with reduced effectiveness when compared to system level implementations