Sonar spectrum recognition chip designed by evolutionary algorithm

An evolutionary design methodology for sonar spectrum recognition chip is proposed and the prototype chip is developed. In the design, sonar spectrum data are transformed to truth-tables and the truth-tables are evolved to obtain generalization capability by using genetic algorithms. Digital circuits are designed by synthesizing the evolved truth-tables. Parallelism in the data can be embedded in the circuits directly by this direct hardware implementation technique of the sonar spectrum data. The circuit size of the developed chip was 4,134 gates, and this was small enough to be implemented onto a standard FPGA (field programmable gate array) chip. Operation speed of the chip was less than 1.0 micro-second per spectrum. Moreover the chip achieved the recognition accuracy of 91.7%, which was higher than those in the backpropagation and the k-NN algorithm