Estimating burn-in fall-out for redundant memory

Integrated circuits can exhibit significant early life or infant mortality failures. Methods to estimate and/or reduce the number of such failures are therefore of great interest to industry. Applications employing multi-chip modules (MCMs), where several die must be independently reliable, are particularly vulnerable to early life failures. Maximizing the reliability of each die is therefore of significant importance. This paper presents an integrated yield-reliability model that allows one to estimate the number of burn-in failures for repairable memory chips, a common component in many MCMs. Since defects in integrated circuits tend to cluster, memory chips that have been repaired have a greater chance of containing a latent defect than chips with no repairs. The result is a higher incidence of infant mortality failure among memory chips that have been repaired