Stability and Static Noise Margin Analysis of Low-Power SRAM

Author

Keerthi, Rajasekhar ; Chen, Chein-in Henry

Author_Institution

Dept. of Electr. Eng., Wright State Univ., Dayton, OH

fYear

2008

fDate

12-15 May 2008

Firstpage

1681

Lastpage

1684

Abstract

To overcome the read data destruction and to gain stability at Iow-V_DD a seven-transistor (7T) SRAM cell is implemented and compared with the conventional six-transistor (6T) SRAM cell. To illustrate the robust performance of an 8-bit SRAM statistical simulation and data analysis by considering the process variations and mismatch was conducted for every operation of the 8-bit SRAM. The measurement results show that the static noise margin (SNM) of the 7T SRAM cell is better than that of the 6T SRAM cell. The stability of the 8-bit 7T SRAM at low-V_DD is also proved by testing the SRAM at 720 mV.

Keywords

CMOS integrated circuits; MOSFET; SRAM chips; circuit stability; data analysis; integrated circuit design; integrated circuit noise; low-power electronics; statistical analysis; 8-bit 7T SRAM cell stability; 8-bit SRAM statistical simulation; circuit stability analysis; conventional 6T SRAM cell comparison; data analysis; low-power SRAM design; read data destruction; static noise margin analysis; submicron CMOS design; voltage 720 mV; Delay; Driver circuits; Instrumentation and measurement; Inverters; MOSFETs; Random access memory; Stability analysis; Switches; Threshold voltage; USA Councils; SRAM; stability; static noise margin (SNM);

fLanguage

English

Publisher

ieee

Conference_Titel

Instrumentation and Measurement Technology Conference Proceedings, 2008. IMTC 2008. IEEE

Conference_Location

Victoria, BC

ISSN

1091-5281

Print_ISBN

978-1-4244-1540-3

Electronic_ISBN

1091-5281

Type

conf

DOI

10.1109/IMTC.2008.4547314

Filename

4547314