On reducing the target fault list of crosstalk-induced delay faults in synchronous sequential circuits

Author

Keller, Keith J. ; Takahashi, Hiroshi ; Saluja, Kewal K. ; Takamatsu, Yuzo

Author_Institution

Wisconsin Univ., Madison, WI, USA

fYear

2001

fDate

2001

Firstpage

568

Lastpage

577

Abstract

This paper describes a method of identifying a set of crosstalk-induced delay faults which may need to be tested in synchronous sequential circuits. In this process, the false crosstalk-induced delay faults that need not (and/or can not) be tested in synchronous sequential circuits are also identify. Our method classifies the pairs of aggressor and victim lines, using topological information and timing information, to deduce a set of faults that need to be tested in a sequential circuit. Experimental results for ISCAS´89 benchmark circuits show that the lists of the target faults obtained by the proposed method are sufficiently smaller than the sets of all possible combinations of faults

Keywords

crosstalk; delays; fault diagnosis; integrated circuit interconnections; integrated circuit testing; logic testing; sequential circuits; ISCAS´89 benchmark circuits; aggressor/victim line pairs; crosstalk-induced delay faults; false crosstalk-induced delay faults; fault set deduction; sequential circuit; synchronous sequential circuits; target fault list reduction; targetfaults; timing information; topological information; Benchmark testing; Circuit faults; Circuit testing; Crosstalk; Delay effects; Fault diagnosis; Sequential analysis; Sequential circuits; Timing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2001. Proceedings. International

Conference_Location

Baltimore, MD

ISSN

1089-3539

Print_ISBN

0-7803-7169-0

Type

conf

DOI

10.1109/TEST.2001.966675

Filename

966675