Enhanced reduced pin-count test for full-scan design

Author

Vranken, Harald ; Waayers, Tom ; Fleury, Hervé ; Lelouvier, David

Author_Institution

IC Design - Digital Design & Test, Philips Res. Lab., Eindhoven, Netherlands

fYear

2001

fDate

2001

Firstpage

738

Lastpage

747

Abstract

This paper presents enhanced reduced pin-count test (E-RPCT) for low-cost test. E-RPCT is an extension of traditional RPCT for circuits in which a large number of digital IC pins is multiplexed for scan. The basic concept of E-RPCT is to provide access to the internal scan chains via an IEEE 1149.1 compatible boundary-scan architecture, instead of direct access via the IC pins. The boundary-scan chain performs serial/parallel conversion of test data. E-RPCT also provides I/O wrap to test non-contacted pins. The paper presents E-PPCT for full-scan design, as well as for full-scan core-based design

Keywords

automatic test equipment; boundary scan testing; built-in self test; design for testability; digital integrated circuits; integrated circuit economics; integrated circuit testing; ATE; BIST; DFT; I/O wrap; IEEE 1149.1 compatible boundary-scan architecture; boundary-scan chain; digital IC pins multiplexing; enhanced reduced pin-count test; full-scan core-based design; full-scan design; internal scan chains; low-cost test; serial/parallel conversion; Circuit testing; Cost function; Design for testability; Digital integrated circuits; Electronic equipment testing; Integrated circuit testing; Laboratories; Performance evaluation; Pins; Semiconductor device testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2001. Proceedings. International

Conference_Location

Baltimore, MD

ISSN

1089-3539

Print_ISBN

0-7803-7169-0

Type

conf

DOI

10.1109/TEST.2001.966695

Filename

966695