• DocumentCode
    1915280
  • Title

    Moving from mixed signal to RF test hardware development

  • Author

    Ferrario, John ; Wolf, Randy ; Ding, Hanyi

  • Author_Institution
    RF & Analog Test Dev. Organ., IBM Corp., Essex Junction, VT, USA
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    948
  • Lastpage
    956
  • Abstract
    A robust RF board design methodology is critical to containing costs, maintaining schedules and providing RF IC customers´ adequate RF test coverage in high volume production for a test development organization. In this paper, a new, robust methodology is described to allow an organization to consistently generate high quality RF test hardware solutions, which will work the first time. This methodology was adopted in the RF IC test development organization in IBM in January of 2000 to address the high demand for unique RF IC test solutions and the complexity involved in the reliable development of high frequency test hardware. The methodology has been demonstrated to allow the test engineer to address the technical issues with RF signals and RF IC´s prior to building the hardware. This saves time, money and sets an appropriate level of expectation with the RF IC design team on what is feasible to test. The methodology can also be extended and applied to improve the reliability of the high frequency logic or networking test hardware development process
  • Keywords
    UHF circuits; UHF integrated circuits; circuit CAD; circuit layout CAD; circuit simulation; integrated circuit design; integrated circuit testing; printed circuit design; printed circuit testing; 3D RF simulation capability; ADS HFSS tool; CAD tool; IBM; RF IC test development organization; RF test coverage; RFIC design; high frequency test hardware; high quality RF test hardware solutions; high volume production; layout parasitic components; robust RF board design methodology; Costs; Design methodology; Hardware; Integrated circuit testing; Logic testing; RF signals; Radio frequency; Radiofrequency integrated circuits; Robustness; Scheduling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 2001. Proceedings. International
  • Conference_Location
    Baltimore, MD
  • ISSN
    1089-3539
  • Print_ISBN
    0-7803-7169-0
  • Type

    conf

  • DOI
    10.1109/TEST.2001.966719
  • Filename
    966719