Boolean and current detection of MOS transistor with gate oxide short

Author

Renovell, M. ; Gallière, J.M. ; Azaïs, F. ; Bertrand, Y.

Author_Institution

Lab. d´´Informatique Robotique Microelectronique de Montpellier, Univ. de Montpellier II: Sci. et Techniques du Languedoc, France

fYear

2001

fDate

2001

Firstpage

1039

Lastpage

1048

Abstract

We study the voltage and current behavior of Gate Oxide Short faults due to pinholes in the gate oxide. Our objective is to give a detailed analysis of the behavior of the GOS defect taking into account random parameters such as the GOS resistance, the GOS location and the GOS size. To facilitate an accurate analysis, we use a bi-dimensional array, and, since a complete analysis is desired, we derive characteristics of the GOS as a function of its resistance, location and size. Finally, we validate the model has been validated through measurements of GOS intentionally injected into a designed and manufactured circuit

Keywords

CMOS integrated circuits; MOSFET; fault simulation; integrated circuit reliability; semiconductor device models; Boolean detection; CMOS ICs; MOS transistor; bi-dimensional array; current detection; defect random parameters; gate oxide pinholes; gate oxide short fault detection; Circuit faults; Circuit simulation; Circuit testing; DH-HEMTs; Electrical resistance measurement; MOSFETs; Manufacturing processes; Robots; Virtual manufacturing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2001. Proceedings. International

Conference_Location

Baltimore, MD

ISSN

1089-3539

Print_ISBN

0-7803-7169-0

Type

conf

DOI

10.1109/TEST.2001.966730

Filename

966730