DocumentCode
1915681
Title
Testing for resistive opens and stuck opens
Author
Li, James C M ; Tseng, Chao-Wen ; McCluskey, E.J.
Author_Institution
Center for Reliable Comput., Stanford Univ., CA, USA
fYear
2001
fDate
2001
Firstpage
1049
Lastpage
1058
Abstract
This paper studies the behavior of stuck and resistive open defects. The effects on test results of three test conditions (supply voltage, speed, temperature) as well as test patterns applied are evaluated. Diagnosis schemes for stuck and resistive opens are also presented. Five Murphy chips are diagnosed as having stuck open defects and one chip is diagnosed as having a resistive open defect. Their experimental data match our expectations for stuck opens and resistive opens
Keywords
automatic test pattern generation; fault diagnosis; integrated circuit testing; logic testing; timing; ATPG tools; Boolean diagnosis; IDDQ testing; Murphy chips; diagnosis schemes; fault simulation; resistive open defects; stuck open defects; supply voltage; test conditions; test patterns; test speed; test temperature; Chaos; Circuit faults; Circuit testing; Cyclic redundancy check; Delay effects; Silicides; Temperature dependence; Timing; Voltage; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2001. Proceedings. International
Conference_Location
Baltimore, MD
ISSN
1089-3539
Print_ISBN
0-7803-7169-0
Type
conf
DOI
10.1109/TEST.2001.966731
Filename
966731
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