Fast test generation for circuits with RTL and gate-level views

In this paper, we propose a simple two-pass strategy that couples register-transfer level (RTL) test generation with gate-level sequential test generation through fault lists. We motivate this approach by showing that faults found hard-to-test by gate-level sequential test generators are often easily testable at the RTL. Likewise, modules found symbolically untestable at the RTL have many of their faults testable at the gate level. Therefore, a two-pass strategy, which runs a fast RTL test generator followed by a gate-level sequential test generator on the remaining untested faults, can leverage off the strengths of each test generator. No modifications are necessary to the source code of either test generator to make this approach work. This makes it particularly attractive to industrial test flows, where the available gate-level test generator may be from a commercial vendor. This is in contrast to many hierarchical test generation techniques where there is significant interdependence between test generation at the register transfer and gate levels. For several benchmark circuits, we experimentally studied the performance of the two-pass approach using a symbolic RTL test generator, TAO, and efficient gate-level test generators, HITEC and SEST. Experimental results show that the proposed two-pass approach achieves a maximum speedup of 103X over a single-pass gate-level sequential test generator. The average speedup was 38X. No design for testability modifications were assumed for the circuits