• DocumentCode
    1915741
  • Title

    Combinational test generation for various classes of acyclic sequential circuits

  • Author

    Kim, Yong Chang ; Agrawal, Vishwani D. ; Saluja, Kewal K.

  • Author_Institution
    Wisconsin Univ., Madison, WI, USA
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    1078
  • Lastpage
    1087
  • Abstract
    It is known that a class of acyclic sequential circuits called balanced circuits can be tested by combinational ATPG. The first contribution of this paper is a modified and efficient combinational single fault ATPG method for any general (not necessarily balanced) acyclic circuit. Without inserting real hardware, we create a "balanced" ATPG model of the circuit in which all reconverging paths have the same sequential depth. Some primary inputs are duplicated and each combinational A TPG vector for this model circuit is transformed into a test sequence. Although no time-frame expansion is used, a small set of faults still map onto multiple faults. Those are identified and dealt with again by the single fault combinational A TPG. The results show nearly an order of magnitude or greater saving in the A TPG CPU time over sequential ATPG. The second contribution consists of new partial-scan algorithms to obtain three subclasses of acyclic circuits, namely, internally balanced, balanced, and strongly balanced, which have been described in the literature. Results on ISCAS \´89 circuits show that such structures require extra scan overhead, sometimes almost approaching that of full-scan, and their advantages in ATPG are marginal considering the present contribution
  • Keywords
    automatic test pattern generation; integrated circuit testing; integrated logic circuits; sequential circuits; DFT methods; acyclic sequential circuits; balanced circuits; combinational ATPG vector; combinational model; combinational single fault ATPG method; internally balanced circuits; partial-scan algorithms; scan overhead; strongly balanced circuits; test generation method; test sequence; Automatic test pattern generation; Circuit faults; Circuit testing; Combinational circuits; Content addressable storage; Electrical fault detection; Fault detection; Flip-flops; Sequential analysis; Sequential circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 2001. Proceedings. International
  • Conference_Location
    Baltimore, MD
  • ISSN
    1089-3539
  • Print_ISBN
    0-7803-7169-0
  • Type

    conf

  • DOI
    10.1109/TEST.2001.966734
  • Filename
    966734