Effects of drain engineering on 0.35 μm NMOS Hot-Carrier degradation

Author

Paulzen, G.M. ; Woltjer, R. ; Montree, A.H. ; Politiek, J.

Author_Institution

Philips Res. Labs., Eindhoven, Netherlands

fYear

1993

fDate

13-16 Sept. 1993

Firstpage

817

Lastpage

820

Abstract

The Large-Angle-Tilted-Implanted-Drain structure (LATID) has been shown to alleviate hot-carrier induced degradation in NMOSFETs. In a comparison of conventional drain, LDD and several different 0.35 μm LATID NMOSFETs we show that a reduced avalanche multiplication factor and a reduced influence of the generated interface states contribute to this improved hot-carrier reliability. The maximum supply voltage that guarantees less than 10% degradation of the transconductance in 10 years as a result of a hot-carrier stress can thus be increased from 2.7 Volts for the conventional drain and 3.3 Volts for the LDD to 4.8 Volts for the 80 keV LATID 0.35 μm NMOSFET.

Keywords

MOSFET; hot carriers; semiconductor device reliability; LATID NMOSFET; LDD; NMOS hot-carrier degradation; drain engineering effects; electron volt energy 80 keV; hot-carrier reliability; hot-carrier stress; large-angle-tilted-implanted-drain structure; reduced avalanche multiplication factor; size 0.35 mum; voltage 2.7 V; voltage 3.3 V; voltage 4.8 V; Charge pumps; Degradation; Hot carrier effects; Hot carriers; Interface states; MOS devices; MOSFETs; Stress; Transconductance; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid State Device Research Conference, 1993. ESSDERC '93. 23rd European

Conference_Location

Grenoble

Print_ISBN

2863321358

Type

conf

Filename

5435614