• DocumentCode
    1916071
  • Title

    Yield-reliability modeling for fault tolerant integrated circuits

  • Author

    Barnett, Thomas S. ; Singh, Adit D. ; Nelson, Victor P.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Auburn Univ., AL, USA
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    29
  • Lastpage
    38
  • Abstract
    An integrated yield-reliability model for defect tolerant integrated circuits is presented that allows one to estimate the yield following both wafer probe and burn-in testing. The model is based on the long observed clustering of defects and the experimentally verified relation between defects causing wafer probe failures and defects causing infant mortality failures. The two-parameter negative binomial distribution is used to describe the distribution of defects over a semiconductor wafer. The clustering parameter α, while known to play a key role in accurately determining wafer probe yields of defect tolerant chips, is shown for the first time. to play a similar role in determining burn-in fall-out. Numerical results indicate that the number of infant mortality failures predicted by the clustering model can differ significantly from calculations that ignore clustering
  • Keywords
    binomial distribution; failure analysis; fault tolerance; integrated circuit modelling; integrated circuit reliability; integrated circuit testing; integrated circuit yield; burn-in fall-out; burn-in testing; clustering parameter; defect clustering; defect distribution; defect tolerant integrated circuits; fault tolerant ICs; infant mortality failures; integrated yield-reliability model; numerical results; reliability yield; semiconductor wafer; two-parameter negative binomial distribution; wafer probe failures; yield estimation; Circuit testing; Fault tolerance; Fault tolerant systems; Integrated circuit modeling; Integrated circuit reliability; Integrated circuit yield; Probes; Production; Redundancy; Semiconductor device modeling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Defect and Fault Tolerance in VLSI Systems, 2001. Proceedings. 2001 IEEE International Symposium on
  • Conference_Location
    San Francisco, CA
  • ISSN
    1550-5774
  • Print_ISBN
    0-7695-1203-8
  • Type

    conf

  • DOI
    10.1109/DFTVS.2001.966749
  • Filename
    966749