A Balanced Ternary Multiplication Circuit Using Recharged Semi-Floating Gate Devices

Author

Gundersen, Henning ; Berg, Yngvar

Author_Institution

Dept. of Informatics, Oslo Univ.

fYear

2006

fDate

Nov. 2006

Firstpage

205

Lastpage

208

Abstract

This paper presents a multiplier circuit using balanced ternary (BT) notation. The multiplier can multiply both negative and positive numbers, which is one of the advantage able properties of the balanced ternary numbering systems. By using balanced ternary notation, it is possible to take advantage of carry free multiplication, which is exploited in designing a fast multiplier circuit. The circuit is implemented with recharged semi-floating gate (RSFG) devices. The circuit operates at 1 GHz clock frequency at a supply voltage of only 1.0 Volt. The circuit is simulated by using CadenceregAnalog Design Environment, with CMOS090 process parameters, a 90nm general purpose bulk CMOS process from STMicroelectronics with 7 metal layers

Keywords

CMOS logic circuits; circuit simulation; floating point arithmetic; logic gates; multiplying circuits; 1 GHz; 90 nm; CMOS090 process parameters; Cadence Analog Design Environment; STMicroelectronics; balanced ternary multiplication circuit; balanced ternary notation; circuit simulation; metal layers; multiplier circuit; recharged semifloating gate devices; Application software; Arithmetic; CMOS process; Circuit simulation; Clocks; Frequency; Informatics; Microelectronics; Project management; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Norchip Conference, 2006. 24th

Conference_Location

Linkoping

Print_ISBN

1-4244-0772-9

Type

conf

DOI

10.1109/NORCHP.2006.329211

Filename

4126982