• DocumentCode
    1918028
  • Title

    System-in-Package design/testing in memory package

  • Author

    Chen, Scott

  • Author_Institution
    ASE, China
  • fYear
    2007
  • fDate
    3-5 Dec. 2007
  • Firstpage
    1
  • Lastpage
    1
  • Abstract
    Summary form only given. Miniaturization, electric performance and cost have drove the package thinner and thinner. System-in-package (SIP) and system-on-chip (SOC) are two competitive solutions. SIP is becoming the mainstream in assembly, which is able to short the design cycle time and speed up the new product introduction, especially in the mobile phone, hand held product and memory products. Stack dice, PoP (package-on-package) is mature and has been widely and growing up the market share. Embedded dice/substrate, fan-out-WLCSP, and TSV (through silicon via) are coming soon. Many new technology, especially for memory has been developed, they will be discussed during the sections.
  • Keywords
    integrated circuit testing; system-in-package; system-on-chip; memory package testing; package-on-package; stack dice; system-in-package; system-on-chip; Assembly; Chemical engineering; Chemical technology; Costs; Mobile handsets; Packaging; Silicon; System testing; System-on-a-chip; Through-silicon vias;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Memory Technology, Design and Testing, 2007. MTDT 2007. IEEE International Workshop on
  • Conference_Location
    Taipei
  • ISSN
    1087-4852
  • Print_ISBN
    978-1-4244-1656-1
  • Electronic_ISBN
    1087-4852
  • Type

    conf

  • DOI
    10.1109/MTDT.2007.4547601
  • Filename
    4547601