Performance analysis of an ATM switch capable of supporting multiclass traffic

The future ATM based B-ISDN is expected to accommodate multiclass traffic in which each class demands peculiar performance requirements in terms of delay and packet loss. In order to cope with such requirements, an ATM switch must be designed to provide low delay and low packet loss. This can be achieved by incorporating priority mechanisms in which priority for service is granted to the most delay-sensitive traffic, and priority to occupy buffer space is given to the most loss-sensitive traffic. The authors examine the performance of a multiplane switch architecture that is capable of supporting multiclass traffic. Performance measures such as mean delay and switch throughput for each class are presented