Smart sampling for risk reduction and delay optimisation

Semiconductor manufacturing processes are very long and complex. They need several hundreds individual steps to produce the final component. Early detection of potential defects or losses is a must to prevent major losses. Metrology is thus a key step in the fabrication line. Whereas a 100% inspection rate would be ideal in theory, the cost of the measurement tools hence cycle time losses due to this measurements would completely inhibit such an approach. This paper studies the impact of the reduction of the inspection sampling rate on performances of the production system. The evolution of the Wafer at Risk (W@R) is used as a performance indicator of the sampling strategy. The process-to-metrology delay is also considered in order to evaluate the risk exposure for process tools.