DocumentCode
1921513
Title
Early sample test technique
Author
Bin Sahari, Muhammad Sadiq ; Ain, Abu Khari Bin A ; Ghee, Khor Jeen
fYear
2010
fDate
3-5 Oct. 2010
Firstpage
441
Lastpage
444
Abstract
Classical test pattern generator (TPG) only concern about producing maximum length of test vector. It does not consider the previous (history) of test vectors which have been generated in producing next test vectors. As a result, succeeding test vector may capture the same fault which resulted in low accumulated fault coverage. In this paper we introduced a new approach for testing both combinational circuits and sequential circuits with the aim to highlight on the importance to consider previous test vectors which have been generated in trying to capture different faults as the generation proceeds to produce consequence test vector. The proposed test method also manages to produce high fault coverage even though the test was sampled early without the need to wait till the last clock. Several experiments have been carried out on ISCAS benchmarks circuit and the results were compared with different test methods. The proposed test method proved effective, producing high fault coverage with a limited number of test vectors.
Keywords
automatic test pattern generation; built-in self test; combinational circuits; logic testing; sequential circuits; ISCAS benchmarks circuit; combinational circuits; early sample test technique; fault coverage; sequential circuits; test pattern generator; test vector; Built-in self-test; Circuit faults; Clocks; Combinational circuits; History; Sequential circuits; Antirandom (AR); Built-in self test (BIST); Test pattern generator (TPG);
fLanguage
English
Publisher
ieee
Conference_Titel
Industrial Electronics & Applications (ISIEA), 2010 IEEE Symposium on
Conference_Location
Penang
Print_ISBN
978-1-4244-7645-9
Type
conf
DOI
10.1109/ISIEA.2010.5679426
Filename
5679426
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