VLSI parallel and distributed computation algorithms for discrete cosine transform processors

A VLSI parallel and distributed computation algorithm has been proposed and mapped onto a VLSI architecture for a 1-D discrete cosine transform (DCT) involving the symmetry property. In this 1-D DCT processor architecture, there are (log₂N+1) DCT processor units (PUs) required for computation of a frame of N-point data with a time complexity of O(N). Further, a 2-D DCT processor architecture has been proposed with the input buffer of an (M×1) 1-D N-point DCT processor array required for computation of the M frames of N-point input data and the output buffer of a (1×N ) 1-D M-point DCT processor array required for permutation of the N frames of M-point output data, so that the total number of DCT PUs require is (M(log₂N+1)+N(log₂M +1)) with a time complexity of O(M+N). Both of the 1-D and 2-D DCT processor architectures can be controlled by firmware; hence they are more flexible, efficient, and fault tolerant and, therefore, very suitable for VLSI implementation