Suppression of CoSix Induced Leakage Current Using Novel Capping Process for Sub-0.10um node SRAM Cell Technology

Author

Kwon, H.S. ; Hwang, B.J. ; Cho, W.S. ; Chang, C.S. ; Kim, S.B. ; Park, Y. ; Ihm, H. ; Park, J.K. ; Kang, H.S. ; Jeong, J.H. ; Park, J.B. ; Jang, Y.C. ; Jung, S.M. ; Kim, Kinam

Author_Institution

Semiconductor R&D Center, Samsung Electronics, Kyungki-Do, Korea (South)

fYear

2002

fDate

24-26 September 2002

Firstpage

195

Lastpage

198

Keywords

Annealing; Diodes; Etching; Fabrication; Leakage current; Random access memory; Silicidation; Silicides; Space technology; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research Conference, 2002. Proceeding of the 32nd European

Print_ISBN

88-900847-8-2

Type

DOI

10.1109/ESSDERC.2002.194903

Filename

1503833

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