Macro block based FPGA floorplanning

This paper describes the floorplanning for FPGA based designs. In order to perform placement for very large designs, the currently followed approach of placing flat netlists is extremely time consuming. Also, managing large data sets, as in flat netlist files, is not trivial for performance driven designs. In this paper we describe an approach for the constraint-based FPGA floorplanning of flexible and fixed macro blocks. Our approach is to construct a floorplan of small area that respects the input constraint set. The input constraint set is derived from topological placement of the macro blocks based on both FPGA architectural constraints and ASIC design. Experimental results on FPGA floorplanning are also presented for large benchmark examples