Verification of a subtractive radix-2 square root algorithm and implementation

Many modern microprocessors implement floating point square root hardware using subtractive algorithms. Such processors include the HP PA7200, the MIPS R4400, and the Intel Pentium. The Intel Pentium division bug highlights the importance of verifying such implementations. In this paper we discuss the verification of a radix-2 square root unit similar to that used in the MIPS R4400. The verification is done by theorem proving to bridge the gap between the algorithm and the implementation. At the top level, we verify that a subtractive, non-restoring algorithm correctly calculates the square root function. We then show a series of optimizing transformations that refine the top level algorithm into the hardware implementation. Each transformation can be verified. We show the transformation of the top level proof to a level that is closer to the hardware implementation. The implementation is at the RTL level, and consists of a structural description of the hardware including an adder/subtracter, simple combinational hardware and some registers