A graph-theoretic approach for register file based synthesis

With the increasing use of register files as storage elements in integrated circuits, the problem of assigning data variables to ports of register files has assumed significance. The assignment involves simultaneous optimization of several cost functions, namely, number of register files, number of registers and access ports per register file, and the interconnect both internal and external to memories. In this paper, we refer to multiplexers, busses, and tristate switches when we refer to interconnect. The objective of this paper is to describe graph-theoretic optimization algorithms for the assignment problem. The allocation system described in this paper (SOUPS) accepts a scheduled data flow graph as input and performs (i) assignment of variables to a minimal number of resisters, (ii) assignments of registers to a minimal number of register files, (iii) assignment of registers to ports of the register files using minimal interconnect within the register files, and (iv) assignment of ports of the register files to terminals of functional modules using minimal interconnect outside the register files. We describe experimental results on several benchmark problems