A floating-point fused FFT butterfly arithmetic unit with Merged Multiple-Constant Multipliers

This paper examines a low-power consumption 1024 point floating-point fused FFT realized with a Multiple-Constant Multiplier (MCM) and with a Merged Multiple-Constant Multiplier (MMCM). The FFT is constructed using Radix-2 butterfly operations that are implemented with MCMs and with MMCMs to reduce the power consumption and area. Conventional MCMs perform the significand multiplication, but with relatively low precision. To enhance the precision, a new architecture of the butterfly unit has been designed and implemented with MMCMs. The new architecture reduces the error by 65% compared to a fused butterfly unit with MCMs at a slight cost in area and power consumption.