Development of read-out circuit and level 2 buffering for multi-channel time measurement chip

The authors describe the design and development of the read-out circuit and level two buffering for a multichannel time measurement chip, L21. The current design interfaces a four-channel version of the time measurement cell with the next level in the data acquisition chain, the data collection chip, for the read-out of the SDC (Solenoidal Detector Collaboration) straw tracking detector. The entire chip was implemented as a standard cell design, except for a full-custom dual-port embedded SRAM (static random-access memory). To verify the logical functionality of the design it was simulated using Verilog. Timing simulations were done with Hspice on blocks of up to 7000 transistors to verify the operation of certain critical high-speed interconnects. The chip was submitted for fabrication in a 1.2 μm n-well process and measured 12 mm²