• DocumentCode
    1931265
  • Title

    An algorithm for multiplication modulo (2∧N-1)

  • Author

    Wang, Zhongde ; Jullien, G.A. ; Miller, W.C.

  • Author_Institution
    VLSI Res. Group, Windsor Univ., Ont., Canada
  • Volume
    3
  • fYear
    1996
  • fDate
    18-21 Aug 1996
  • Firstpage
    1301
  • Abstract
    This paper proposes an efficient algorithm for multiplication modulo (2N-1). To achieve high speed, the Wallace tree is adopted for the multiplier. The Wallace tree multiplier exhibits a more regular structure than binary Wallace tree multipliers, and comparisons with published designs demonstrates advantages of our multiplier architecture in both speed and hardware
  • Keywords
    multiplying circuits; residue number systems; trees (mathematics); Wallace tree multiplier; algorithm; high speed architecture; multiplication modulo (2∧N-1); Arithmetic; Hardware; Logic; Table lookup; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1996., IEEE 39th Midwest symposium on
  • Conference_Location
    Ames, IA
  • Print_ISBN
    0-7803-3636-4
  • Type

    conf

  • DOI
    10.1109/MWSCAS.1996.593165
  • Filename
    593165
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1931265