Enhanced LEON3 Low Power IP Core for DSM technologies

Power consumption is one of the most important factor in a modern embedded System-on-Chip´s (SoC´s) design. Increasing computation complexity and incessant growth of clock frequency reveals the necessity for dynamic and smart utilization of the available hardware resources. The paper presents Enhanced LEON3 Low Power IP Core with superscalar abilities and Low Power Management Unit (LPMU). In comparison with the original LEON3 IP core, the new one may execute up to two instructions per cycle and dynamically manage incorporated power domains. Enhanced LEON3LP IP core was synthesized using TSMC 90 nm CMOS technology.