• DocumentCode
    1932731
  • Title

    Switching performance optimization for high frequency high power 3-level neutral point clamped phase leg

  • Author

    Yang Jiao ; Sizhao Lu ; Lee, Fred C.

  • Author_Institution
    Bradley Dept. of Electr. & Comput. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
  • fYear
    2013
  • fDate
    15-19 Sept. 2013
  • Firstpage
    3949
  • Lastpage
    3956
  • Abstract
    A 3-level neutral point clamped (NPC) phase leg was designed and tested as modularized building block for renewable energy grid interface converter. To achieve high switching frequency and high efficiency, the phase leg was carefully designed and evaluated. Different operating modes and switching loops in the phase leg were identified. Double pulse tests were conducted for turn on and off transient of each loop. Various parameters like gate resistance and parasitic inductance were taken into consideration as influential factors to loss and stress. An in-depth analysis of their impact to the switching transient is also given. The distinctive switching characteristics of each switch provide guidance for its gate resistor selection and loss-stress tradeoff. The phase leg loss distribution and system loss for diode clamped and active clamped NPC under different power factors are calculated and compared based on the loss data from experiment. Based on the result, the overall switching performance for 3-level NPC phase leg can be optimized under various operating condition.
  • Keywords
    diodes; losses; optimisation; power factor; power grids; resistors; switching convertors; building block modulation; diode clamped loss system; distinctive switching transient characteristics; double pulse testing; gate resistance; gate resistor selection; high frequency high power 3-level neutral point clamped phase leg; loss-stress tradeoff; parasitic inductance; phase leg loss distribution; power factor calculation; renewable energy grid interface converter; switching frequency loop; switching performance optimization; Inductance; Insulated gate bipolar transistors; Logic gates; Resistors; Stress; Switches; Transient analysis;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Energy Conversion Congress and Exposition (ECCE), 2013 IEEE
  • Conference_Location
    Denver, CO
  • Type

    conf

  • DOI
    10.1109/ECCE.2013.6647224
  • Filename
    6647224