III-V material and device aspects for the monolithic integration of GaAs devices on Si using GaAs/Si low temperature wafer bonding

Author

Georgakilas, A. ; Alexe, M. ; Deligeorgis, G. ; Cengher, D. ; Aperathitis, E. ; Androulidaki, M. ; Gallis, S. ; Hatzopoulos, Z. ; Halkias, G.

Author_Institution

Dept. of Phys., Crete Univ., Greece

Volume

1

fYear

2001

fDate

2001

Firstpage

239

Abstract

A new process for wafer scale integration of GaAs optoelectronic devices with Si integrated circuits has been investigated, based on low temperature bonding of epitaxial GaAs wafers onto planarized fully processed CMOS/BiCMOS wafers. The basic process flow and the most important aspects of the work concerning the III-V material and devices are presented

Keywords

BiCMOS integrated circuits; CMOS integrated circuits; III-V semiconductors; elemental semiconductors; gallium arsenide; integrated optoelectronics; semiconductor epitaxial layers; silicon; wafer bonding; wafer-scale integration; CMOS/BiCMOS wafer; GaAs epitaxial wafer; GaAs optoelectronic device; GaAs-Si; III-V material; Si integrated circuit; Si substrate; low temperature wafer bonding; monolithic integration; planarization; wafer scale integration; BiCMOS integrated circuits; CMOS integrated circuits; CMOS process; Gallium arsenide; III-V semiconductor materials; Monolithic integrated circuits; Optoelectronic devices; Temperature; Wafer bonding; Wafer scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Conference, 2001. CAS 2001 Proceedings. International

Conference_Location

Sinaia

Print_ISBN

0-7803-6666-2

Type

conf

DOI

10.1109/SMICND.2001.967455

Filename

967455