Evolving defect tolerant structures for FPGA architectures

The challenge of production defects for integrated circuits increases as feature size decreases. One approach to tolerating such production defects is to apply redundancy techniques. In this work, an evolutionary algorithm is applied in the search for new efficient structures for FPGA architectures to provide enhanced tolerance to production defects. The paper presents the results so far and discusses some of the more practical challenges facing evolutionary techniques for such real-world applications.