Stacked CMOS Technology by Local Overgrowth (LOG)

A new process is presented for building stacked CMOS transistors with high device quality. Device deterioration on bulk devices was minimized by reduced temperature processing for the SOI device, and the use of epitaxial lateral overgrowth to produce the silicon film for top devices improved film quality. The application of chemo-mechanical polishing allowed realization of 0.7¿m silicon films with better than 10% uniformity. NMOS transistors built in the bulk material exhibit 700cm²/Vs mobility and 105mV/dec subthreshold slope, while PMOS devices in the SOI film have surface mobilities of 165cm²Vs and a subthreshold slope of 109mV/dec. Threshold voltages are 0.5V and - 1.5V, respectively.