Design of multiple-valued linear digital circuits for highly parallel k-ary operations

To design highly parallel digital circuits such as an adder and a multiplier, it is difficult to find the optimal code assignment in the nonlinear digital system. On the other hand, the use of the linear concept in digital systems seems to be very attractive because analytical methods can be utilized. For unary operations, the design method of locally computable circuits have been discussed. In this paper, we propose a new design method of highly parallel multiple-valued linear digital circuits for k-ary operations using the concept of identification of input-output graphs by the introduction of multiplicated redundant symbols